CAPPS: A Framework for Power–Performance Tradeoffs in Bus-Matrix-Based On-Chip Communication Architecture Synthesis

On-chip communication architectures have a significant impact on the power consumption and performance on emerging chip multiprocessor (CMP) applications. However, customization of such architectures for an application requires the exploration of a large design space. Designers need tools to rapidly explore and evaluate relevant communication architecture configurations exhibiting diverse power and performance characteristics. The study of an automated framework for fast system-level, application-specific, power-performance tradeoffs in a bus matrix communication architecture synthesis (CAPPS), makes two specific contributions. First, developping energy models for system-level exploration of bus matrix communication architectures. Second, incorporating these models into a bus matrix synthesis flow that enables designers to efficiently explore the power-perfromance design space of different bus matrix configuration.

Here is an example of applying bus matrix on short circuits for generators:




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